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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
SPI TIMING CHARACTERISTICS (Notes 14, 15, Figure 1)
(DV DD = +2.7V to +5.25V, AV DD = +4.75V to +5.25V, V DGND = V AGND = 0, external V REFADC = +2.5V, external V REFDAC = +2.5V,
C REF = 0.1μF, T A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
SCLK High Time
SCLK Low Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
t CP
t CH
t CL
t DS
t DH
62.5
25
25
15
0
ns
ns
ns
ns
ns
SCLK Fall to DOUT Transition
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Rise or Fall to SCLK Rise
CS Pulse-Width High
Last SCLK Rise to CS Rise
t DO
t DV
t TR
t CSS
t CSW
t CSH
C L = 30pF
C L = 30pF
C L = 30pF (Note 16)
12.5
50
0
20
50
50
ns
ns
ns
ns
ns
ns
I 2 C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV DD = +2.7V to +5.25V, AV DD = +4.75V to +5.25V, V DGND = V AGND = 0, external V REFADC = +2.5V, external V REFDAC = +2.5V,
C REF = 0.1μF, T A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Bus Free Time Between a STOP
and START Condition
t BUF
1.3
μs
Hold Time (Repeated) for START
Condition
Setup Time for a Repeated
START Condition
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t HD:STA
t SU:STA
t LOW
t HIGH
t SU:DAT
After this period, the first clock pulse is
generated
0.6
0.6
1.3
0.6
100
μs
μs
μs
μs
ns
Data Hold Time
SDA, SCL Rise Time
SDA, SCL Fall Time
SDA Fall Time
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
Pulse Width of Spikes
Suppressed by the Input Filter
t HD:DAT
t R
t F
t F
t SU:STO
C B
t SP
(Note 17)
Receiving (Note 18)
Receiving (Note 18)
Transmitting (Notes 18, 19)
(Note 20)
(Note 21)
0.004
0
0
20 + 0.1
x C B
0.6
0.9
300
300
250
400
50
μs
ns
ns
ns
μs
pF
ns
6
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